Inviwo is an extendable C++ framework for easy prototyping of interactive applications. It provides a network editor for the designing of data flow networks, i.e. visualization pipelines, which are automatically evaluated and executed to produce output on one or more output processors (typically a canvas). The data flow in such a network runs from top to bottom, and the nodes are referred to as processors. Besides these processors two more first class objects exist. Ports, which are used to exchange data in between processors, and properties, which define the state of a processor.
Processors are the primary objects the user interacts with inside the network editor. Usually, they are dragged from the processor list on the left onto the network editor, before they are connected. Processors receive input data and generate output data through ports, whereby the ports on the top boundary are referred to as inports, and the ports on the bottom boundary are referred to as outports. Each processor has a set of properties, which define its current state. Upon selection of a processor in the network editor, its properties are shown in the property list on the right, where they can be edited.
Processors can exchange information in two ways. First, they can exchange data through their ports, whereby equally colored ports are of same type and can thus exchange data. Port connections can be established by connecting two ports via drag-and-drop. Besides the ports, the properties of a processor can be linked in order to synchronize their values. Links can be established by creating a connection between the semicircles of two processors.
To distinguish processors in a network, they have unique identifiers which can be edited by the user. Initially the identifier will be equal to the type of the processor, which is shown in italic below the identifier. Furthermore, the processor shows whether it is correctly connected through the status light.
Processor network information flow
The data flow in the processor network is a directed acyclic graph (DAG), meaning that data cannot flow back and form a loop. Source processors, i.e. processors without any inports, inject data into the network and sink processors, i.e. processors without any outports, finalizes pipelines within the network. A pipeline can be evaluated when a DAG has been created between source and sink processors as exemplified in its visual abstraction layer representation in the figure below. Network evaluation is performed after data or properties have changed. In practice, the evaluation is separated into an invalidation phase and an evaluation phase. The invalidation phase is triggered as soon as the network is modified and aim to determine which part of the network that needs evaluation. As an example, a property change causes the property to be marked as invalid. The invalidation is propagated to its owner, usually a processor, and then follows the data-flow downwards, leaving invalid states in its path. The invalidation phase ensures that the network evaluation only need to be done once even though there may be many subsequent changes initiated by the first property change. The evaluation iterates over a topologically sorted list of all the processors in the processor network and evaluates all the invalid processors. Note that each outport caches data by default, which means that only the processor subgraph affected by the change need to be evaluated. The topological ordering and evaluation logic is taken care of by a processor network evaluator.
Property link flow
It is often necessary to synchronize properties within the processor network. Two different processors may for example use the same camera parameters. Inviwo uses the concept of property links to synchronize properties in different processors. In practice, property links can be implemented by referencing the same value, or copying the value. In Inviwo, the latter approach is used since the use of references limit the possibilities of for example being able to link properties of different types but with the same semantics, i.e. float and double. The property links are allowed to form a general graph, i.e. loops are allowed, as opposed to the data flow network. Infinite looping in property link evaluation is prevented by creating a DAG for each node in the link graph, which also result in efficient link evaluation as a side effect. The visual abstraction layer representation of a property link is a dotted line connecting two processors.
So far, two information flows has been described, a vertical downwards flow formed by the data, and a horizontal flow formed by property links. Events, often initiated by user interaction, form the third information flow in the processor network. Events are propagated upwards in the same path as the data flow, through ports, but in the opposite direction. These three information flows form the core of the processor network and are are illustrated in the figure above.